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About the Role

SiTime is the Precision Timing company, providing MEMS-based Precision Timing solutions that offer greater accuracy, smaller size, and resilience for over 400 applications including AI datacenters, automated driving, and IoT. Our programmable solutions enable customers to differentiate their products with higher performance, smaller size, lower power, and better reliability.

Responsibilities

• Develop precision timing circuit architectures and design innovative circuits with aggressive technical performance specifications, performing transistor-level design and simulations.
• Plan and execute circuit designs addressing demanding frequency stability, phase noise, power consumption, and silicon die area specifications.
• Perform technology, architecture, circuit design, and parametric design trade-offs to achieve spec-compliant designs.
• Ensure first-pass success on Analog CMOS circuit solutions, leveraging SiTime’s innovative MEMS technology.
• Collaborate with Digital Design Engineers, CAD, Systems Engineering, ATE Engineering, and Applications teams for chip design, DFT, DFM, silicon bring-up, and production release.
• Deploy robust design methodology and ensure comprehensive design reviews.
• Supervise and guide Senior Analog Circuit Designers.
• Supervise Analog Circuit Physical Design Layout and edit layouts.
• Perform post-layout parasitic-extraction and back-annotated simulations to validate design across Process, Voltage, and Temperature (PVT).
• Perform requisite Monte Carlo Analysis on key circuits to ensure Six-Sigma quality and yields.
• Participate in silicon prototype bring-up.
• Initiate Design-of Experiments for Root Cause Analysis, investigate anomalous silicon observations across PVT conditions, and propose solutions.
• Drive other projects as needed by management or business needs.

Requirements

• MS Degree in Electrical Engineering, PhD preferred.
• Minimum 10 years of high-performance analog circuit design experience.
• Proven track record in circuit architecture development and technical feasibility studies.
• Proven track record in design partitioning for phase noise / power budgeting.
• Proven track record in writing detailed block-level specifications.
• Proven track record in detailed design, test bench development, and simulation of basic analog building blocks and one or more of the following: ADCs, DACs, Temperature Sensors, PLL, high-speed Operational Amplifiers, On-chip Regulators, Band gap Circuits.
• Expert-level experiential knowledge of architecting and implementing ultra low-jitter, power-efficient Frac-N PLLs.
• Experiential knowledge of ultra-low phase-noise design, power supply noise considerations, device matching, parasitic extraction, signal integrity, and ESD.
• Supervision of Junior and Senior Analog Design Engineers.
• Supervision of layout and editing of critical blocks.
• Chip-level design and verification of complex mixed-signal chips.
• Chip validation, Characterization, Qualification, and adherence to production release.
• 3 years of prior lead/supervisory/managerial experience preferred.
• Passionate, self-starter with strong commitment to flawless execution.
• Curious, with the desire to solve any problem.
• Excellent written and verbal communication skills.
• Ability to work well with others in a fast-paced collaborative team environment.

Skills

• Analog CMOS circuit design
• Transistor-level design
• Circuit simulations
• Frequency stability
• Phase noise
• Power consumption
• Silicon die area
• Technology trade-offs
• Architecture trade-offs
• Circuit design trade-offs
• Parametric design trade-offs
• MEMS technology
• Digital Design
• CAD
• Systems Engineering
• ATE Engineering
• Design for Testability (DFT)
• Design for Manufacturability (DFM)
• Silicon bring-up
• Time-to-production release
• Design methodology
• Design reviews
• Analog Circuit Physical Design Layout
• Post-layout parasitic-extraction
• Back-annotated simulations
• Process, Voltage, Temperature (PVT) validation
• Monte Carlo Analysis
• Six-Sigma quality
• Yield analysis
• Silicon prototype bring-up
• Design-of Experiments (DOE)
• Root Cause Analysis
• ADCs
• DACs
• Temperature Sensors
• PLL
• High-speed Operational Amplifiers
• On-chip Regulators
• Band gap Circuits
• Frac-N PLLs
• Ultra-low phase-noise design
• Power supply noise considerations
• Device matching
• Parasitic extraction
• Signal integrity
• ESD
• Chip-level design
• Mixed-signal chip verification
• Chip validation
• Chip Characterization
• Chip Qualification
• Production release

Location

• Remote

Work Type

• Full-time

Experience Level

• Principal
• Minimum 10 years
• 3 years lead/supervisory/managerial experience preferred

Education Level

• MS Degree in Electrical Engineering
• PhD preferred

Salary/Compensations

• Quarterly bonus tied to innovation goals
• Equity grants

Benefits

• Comprehensive and highly competitive compensation package
• Quarterly bonus
• Equity grants

About the Company

• SiTime is the Precision Timing company.
• Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability.
• MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience.
• Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability.
• With more than 4 billion devices shipped, SiTime is changing the timing industry.

Equal Opportunity

• SiTime is an Equal Opportunity Employer.
• We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law.