Sr. Principal Application Engineer, Customer Engagement at Cadence | Austin, TX, US | Rezi

Sr. Principal Application Engineer, Customer Engagement at Cadence

Sr. Principal Application Engineer, Customer Engagement

Cadence · Austin, TX, US

1 months ago

Sr. Principal Application Engineer, Customer Engagement

Cadence · Austin, TX, US

2 months ago
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About the Role

Utilizing an engineering background, this role provides pre-sales and/or post-sales technical customer support for Electronic Design Automation (EDA) and semiconductor intellectual property (IP), including implementation, training, and maintenance. The position involves developing innovative solutions and custom methodologies for Cadence’s Digital Design and Signoff tools, tailoring company technologies to customer workflows and design performance targets. Analyzing customer requirements and driving adoption of Cadence EDA solutions is key, supported by investigating products, identifying gaps, recognizing needs, and delivering technical presentations and demonstrations.

Responsibilities

  • Provide pre-sales and/or post-sales technical customer support including implementation, training, and maintenance support for Electronic Design Automation (EDA) and semiconductor intellectual property (IP).
  • Develop innovative solutions and custom methodologies to Cadence’s Digital Design and Signoff tools, tailoring company technologies to customer workflows and respective design performance targets.
  • Analyze customer requirements and drive adoption of Cadence EDA solutions by supporting customer investigations, identifying product gaps, recognizing unmet needs, and delivering technical presentations and demonstration.
  • Provide expert-level support by diagnosing and resolving complex issues in Backend Digital Design Implementation, including Synthesis.
  • Mentor customers and internal teams by conducting technical training sessions, workshops, and customized consulting engagements on best practices across RTL-GDSII flows, including methodology development for physical design closure, low power optimization, and design for manufacturability at advanced nodes (2nm-7nm).
  • Provide expertise in the final stages of design processes in custom designs, improving manufacturing, design checks, and testing iterations.
  • Partner with internal engineering and sales teams to influence product enhancements and feature development.
  • Work horizontally across various design teams and Cadence R&D engineers to develop new features for Cadence tools.
  • Gather and establish methodology, best practices, and solutions to increase in-house productivity.
  • Must be available to work on projects at various, unanticipated sites throughout the United States.

Requirements

  • Bachelor’s degree in Electronic Engineering, Electrical Engineering, or related field
  • Minimum twelve (12) years of post-baccalaureate, progressive experience in the job offered or in a related engineering occupation.
  • Application Specific Integrated Circuit digital (ASIC) design flow using Cadence Tools
  • Digital design implementation, Register-Transfer Level (RTL) Synthesis, logic design and synthesis, formal verification, low power design, and timing closure
  • Industry standard Cadence EDA front end digital implementation tools including Genus, Innovus, Voltus and related Cadence technologies
  • Application-Specific Integrated Circuit (ASIC) design using Cadence Joules RTL Design Studio
  • Static Timing Analysis (STA) and Engineering Change Orders (ECOs) to achieve the final design targets
  • Place and route physical design flow using EDA tools
  • Low power design methodologies including power intent description and verification
  • Automation skills using Python, Perl, Tcl, and shell scripting
  • Must be available to work on projects at various, unanticipated sites throughout the United States.

Skills

  • Electronic Design Automation (EDA)
  • Semiconductor intellectual property (IP)
  • Digital Design and Signoff tools
  • Backend Digital Design Implementation
  • Synthesis
  • RTL-GDSII flows
  • Physical design closure
  • Low power optimization
  • Design for manufacturability
  • Advanced nodes (2nm-7nm)
  • Custom designs
  • Python
  • Perl
  • Tcl
  • Shell scripting
  • Application Specific Integrated Circuit digital (ASIC) design
  • Cadence Tools
  • Register-Transfer Level (RTL) Synthesis
  • Logic design and synthesis
  • Formal verification
  • Low power design
  • Timing closure
  • Genus
  • Innovus
  • Voltus
  • Cadence Joules RTL Design Studio
  • Static Timing Analysis (STA)
  • Engineering Change Orders (ECOs)
  • Place and route physical design flow
  • EDA tools

Location

  • United States

Work Type

  • Full-time

Experience Level

  • Minimum twelve (12) years of post-baccalaureate, progressive experience

Education Level

  • Bachelor’s degree in Electronic Engineering, Electrical Engineering, or related field

About the Company

  • Cadence plays a critical role in creating the technologies that modern life depends on.
  • We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
  • Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.
  • Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Equal Opportunity

  • Cadence is proud to be an equal opportunity employer.
  • All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.