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About the Role

Cadence hires and develops leaders and innovators to impact the world of technology. This role involves researching, designing, developing, and testing electronic components and systems for EDA and semiconductor IP.

Responsibilities

• Research, design, develop, and test electronic components and systems for Electronic Design Automation (EDA) and semiconductor intellectual property (IP) employing knowledge of electronic theory and materials properties.
• Interface with customers regarding library development methodologies, including timing characterization, EMIR view generation, physical view generation (LEF, GDS, abstracts, etc.), logical view generation (LIB, CDL, Spectre, etc.), and technology LEF creation for digital tools.
• Scope the level of effort, perform library characterization, generate logical and physical views such as PGV, Verilog, LEF, DSPF, etc., and support validation of the results.
• Support adoption and proliferation of existing customers (on/offsite) to help drive business for Cadence library development tools.
• Work closely with Research and Development (R&D) on tools and methodology improvements.
• Create and contribute technical content for Cadence online support.
• Perform other digital place and route (P&R) tasks as needed by the group.

Requirements

• Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Minimum one (1) year of experience in the job offered or in a related engineering occupation.
• Standard cell library characterization.
• Standard cell library design knowledge, specifically standard cell development to optimize PPA using Cadence characterization tools.
• Utilize Cadence Virtuoso tool Suite and Liberate to standard cell characterization for PPA analysis and optimization for tools and library.
• Characterization of foundation IP library.
• Library comparison and analysis across Process Design Kit (PDK) and foundry.

Skills

• Electronic theory
• Materials properties
• Library development methodologies
• Timing characterization
• EMIR view generation
• Physical view generation (LEF, GDS, abstracts, etc.)
• Logical view generation (LIB, CDL, Spectre, etc.)
• Technology LEF creation
• Digital tools
• Library characterization
• Logical and physical views (PGV, Verilog, LEF, DSPF, etc.)
• Validation of results
• Cadence characterization tools
• Cadence Virtuoso tool Suite
• Liberate
• PPA analysis and optimization
• Foundation IP library characterization
• Library comparison and analysis
• Process Design Kit (PDK)
• Foundry

Location

• Onsite
• Offsite

Work Type

• Telecommuting permitted

Experience Level

• Minimum one (1) year of experience

Education Level

• Master’s degree in Electrical Engineering, Computer Engineering, or related field

About the Company

• Cadence plays a critical role in creating the technologies that modern life depends on.
• We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
• Recognized by Fortune Magazine as one of the 100 Best Companies to Work For.
• Shared passion for solving the world’s toughest technical challenges.
• Dedication to pushing the limits of the industry.
• Drive to do meaningful work.

Equal Opportunity

• All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.