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About the Role

You will work with a global team on the physical design of complex chips and the methodology to enable an efficient and robust design process. Every day, you'll be working hands-on to triage workflows, running RTL code through synthesis and place and route (PnR) tools to create the physical view of the chip, analyzing performance by running timing analysis, and verifying a robust power grid by performing EMIR analysis. There are many sign-off checks that need to happen to verify that the database is ready to move on to the next level, and it's your responsibility to review completed runs for errors or create optimizations from successful runs.

Responsibilities

Work on the physical design of complex chips.
Develop and implement methodologies for an efficient and robust design process.
Triage workflows daily.
Run RTL code through synthesis and place and route (PnR) tools.
Create the physical view of the chip.
Analyze performance by running timing analysis.
Perform EMIR analysis to verify power grid robustness.
Review completed runs for errors.
Create optimizations from successful runs.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields, or the equivalent work experience.
Experience in physical design with a focus on block-level PNR for advanced CMOS process nodes (e.g., 7nm, 5nm, or below).
Working experience with industry-standard EDA tools for physical design, including Cadence Genus and Innovus, and Synopsys Design Compier, IC Compiler and Fusion Compiler.
Working knowledge of static timing analysis tools such as Tempus or PrimeTime.
Working knowledge of EM/IR-Drop/Crosstalk analysis tools like Voltus or PrimeRail is advantageous.
Working knowledge of physical verification and formal verification tools (e.g., Calibre, LEC, Formality) is advantageous.
Willingness to raise your hand and volunteer for learning opportunities.
Must be eligible to access export-controlled information as defined under applicable law.
Candidates are not permitted to use AI tools during interviews.

Skills

Physical design
Block-level PNR
Advanced CMOS process nodes
Cadence Genus
Cadence Innovus
Synopsys Design Compiler
Synopsys IC Compiler
Synopsys Fusion Compiler
Static timing analysis
Tempus
PrimeTime
EM/IR-Drop/Crosstalk analysis
Voltus
PrimeRail
Physical verification
Formal verification
Calibre
LEC
Formality

Location

Austin, TX

Work Type

Full-time
On-site

Experience Level

Experience in physical design with a focus on block-level PNR for advanced CMOS process nodes (e.g., 7nm, 5nm, or below)

Education Level

Bachelor’s degree in Computer Science, Electrical Engineering or related fields, or the equivalent work experience

Salary/Compensations

95,200 - 140,860 USD per annum

Benefits

Employee stock purchase plan with a 2-year look back
Family support programs
Robust mental health resources
Recognition and service awards

About the Company

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.
Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow.
For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Equal Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.