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About the Role

Aion Silicon is seeking an experienced Principal Physical Design Engineer to lead the physical implementation of complex, cutting-edge SoCs and ASICs. This senior technical leadership role is for a recognized Full-Chip Physical Design expert who thrives on solving complex challenges, mentoring engineering teams, and driving successful tape-outs on advanced technology nodes. You will own the complete physical design flow, from RTL/netlist handoff through to final sign-off and GDSII generation, collaborating with global cross-functional teams.

Responsibilities

• Lead full-chip physical implementation for complex SoC and ASIC designs.
• Define and drive chip-level physical design strategies, methodologies, and best practices.
• Coordinate with RTL, STA, DFT, Packaging, Foundry, and EDA partners for design closure.
• Mentor and coach Physical Design engineers, supporting team capability development.
• Review and approve block-level physical design deliverables before integration.
• Lead technical reviews, debug sessions, and closure activities.
• Support recruitment activities and contribute to building a world-class Physical Design team.
• Represent Aion Silicon at industry events, sharing technical expertise and promoting innovation.
• Ensure the team stays at the forefront of industry methodologies, tools, and advanced-node technologies.

Requirements

• 10+ years of Physical Design experience with a proven track record of full-chip delivery.
• Strong expertise in advanced technology nodes (7nm, 5nm, and below).
• Experience delivering multiple complex SoC or ASIC tape-outs.
• Demonstrated leadership experience mentoring and developing engineers.
• Strong customer engagement and stakeholder management skills.
• Excellent communication skills with the ability to influence technical direction across multiple teams.
• Deep expertise in Full-Chip Floorplanning & Integration, including chip-level floorplanning, macro placement, IO ring integration, hierarchical and flat implementation flows, and pin placement, channel planning, and congestion management.
• Deep expertise in Power Planning & Package Integration, including power grid design and optimization, multi-voltage domains and power gating, IR drop and electromigration analysis, and bump planning and package co-design.
• Deep expertise in Clock Tree Synthesis, including multi-domain and multi-level CTS, clock mesh, H-tree and fishbone architectures, skew, latency and jitter optimization, and low-power clocking techniques.
• Deep expertise in Placement, Routing & Timing Closure, including full-chip placement and routing, signal integrity, crosstalk and antenna resolution, MCMM timing analysis, STA sign-off and timing ECO implementation, and hierarchical timing budgeting and closure.
• Deep expertise in Physical Verification & Tape-Out, including DRC, LVS and ERC sign-off, RC extraction and correlation, reliability and noise analysis, and GDSII/OASIS generation and foundry handoff.
• Strong working knowledge of one or more industry-leading tool flows (Synopsys, Cadence, Mentor Calibre).
• Desirable experience with DFT integration and ECO flows, 2.5D/3D-IC and chiplet-based architectures, and advanced packaging technologies.
• Leads through collaboration, trust, and transparency.
• Thrives in a fast-paced environment and enjoys solving complex technical challenges.
• Demonstrates strong ownership and accountability.
• Has a passion for mentoring and developing others.
• Is adaptable, resilient, and able to navigate changing priorities.
• Embodies Aion Silicon's values and contributes positively to our culture.

Skills

• Full-Chip Floorplanning & Integration
• Power Planning & Package Integration
• Clock Tree Synthesis
• Placement, Routing & Timing Closure
• Physical Verification & Tape-Out
• Synopsys (ICC2, Fusion Compiler, PrimeTime, StarRC, ICV)
• Cadence (Innovus, Tempus, Voltus, Genus)
• Mentor Calibre
• DFT integration
• 2.5D/3D-IC and chiplet-based architectures
• Advanced packaging technologies

Location

• Global
• Hybrid

Work Type

• Hybrid
• Full-time

Experience Level

• Principal
• 10+ years

Education Level

• Master's or PhD in a relevant engineering discipline

About the Company

• At Aion Silicon, we're seeking an experienced Principal Physical Design Engineer to lead the physical implementation of complex, cutting-edge SoCs and ASICs.
• Join Aion Silicon and Shape the Future of Semiconductor Innovation.
• At Aion Silicon, you'll work alongside exceptional engineers on some of the industry's most challenging semiconductor projects.
• You'll have the opportunity to influence technical strategy, mentor future talent, and help shape the next generation of silicon solutions.