Impress employers and recruiters.
Choose from hundreds of resume examples.

Target Resume Now

About the Role

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Responsibilities

Define, design and verify ASIC and ASIC subsystems for deployment in Cisco platforms.
Contribute to a multi-disciplined engineering team to meet power, performance, and area goals.
Design, document, and develop ASIC subsystems for high-volume, quality release.
Help define processes, methods, and tools for complex development design and implementation.
Lead the CDC/RDC methodology in Silicon One chips.
Design and implement robust, reusable RTL with CDC/RDC considerations.
Specify comprehensive CDC/RDC check flows and collaborate with the CAD team for implementation.
Review and approve CDC/RDC constraints and waivers.
Perform static glitch analysis.
Improve designs by preventing static glitch hazards.

Requirements

Bachelor's degree with 8+ years of related experience, or Master's degree with 6+ years of related experience, or PhD with 3+ years of related experience.
Prior experience with RTL development skills and experiences.
Prior experience with CDC/RDC concepts and relevant design implementation.
Prior experience maintaining CDC/RDC flow and signing-off constraints and waivers.
Prior experience with static glitch hazards and analysis on synthesis-optimized gate netlists.

Skills

RTL development
CDC/RDC concepts
Static glitch analysis
SDC constraints development
VCS simulation SVA (SystemVerilog Assertions)

Location

U.S.
Canada

Work Type

Full-time

Experience Level

8+ years
6+ years
3+ years

Education Level

Bachelor's degree
Master's degree
PhD

Salary/Compensations

$183,800.00 - $263,600.00 (U.S. and/or Canada)
$183,800.00 - $303,100.00 (New York City Metro Area)
$163,600.00 - $269,800.00 (Non-Metro New York state & Washington state)

Benefits

Medical, dental and vision insurance
401(k) plan with Cisco matching contribution
Paid parental leave
Short and long-term disability coverage
Basic life insurance
Restricted stock units
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year (non-exempt employees)
Flexible vacation time off program (exempt employees)
80 hours of sick time off provided on hire date and each January 1st
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid days per full calendar year to volunteer
Annual bonuses (non-sales roles)
Performance-based incentive pay (sales roles)

About the Company

Cisco is revolutionizing how data and infrastructure connect and protect organizations in the AI era and beyond.
Cisco has been innovating for 40 years to create solutions that power how humans and technology work together across physical and digital worlds.
Cisco's solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Opportunities to grow and build are limitless at Cisco.
Cisco fosters a collaborative environment with empathy to make significant impacts on a global scale.