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About the Role

We are seeking a highly motivated and technically strong ASIC CAD Flow & Infrastructure Engineer to drive the development, deployment, and support of next-generation ASIC design infrastructure. This role is responsible for defining scalable EDA methodologies, automation frameworks, and design flows that enable efficient development of complex SoCs across multiple product generations. The ideal candidate combines deep semiconductor design-flow knowledge with software engineering expertise. The individual will collaborate closely with Design, Physical Design and IT teams to deliver robust, high-performance CAD solutions that improve engineering productivity and design quality.

Responsibilities

Develop and maintain CAD frameworks using Python, Tcl, Shell, and modern software engineering practices
Build flow orchestration systems, dashboards, analytics, and monitoring tools
Develop and maintain automation frameworks for integrating standard-cell libraries, memory macros, and IP blocks across multiple ASIC design and implementation flow entry points
Establish best practices for synthesis and physical implementation
Develop standardized flow frameworks that maximize reusability, maintainability, and automation

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree
At least 5+ years of experience in ASIC CAD, EDA, design methodology, or infrastructure engineering. 8+ years preferred.
Strong understanding of ASIC/SoC development lifecycle from RTL through tapeout
Proficiency in Python and Tcl scripting
Experience with Linux-based development environments
Experience supporting commercial EDA tools from Synopsys, Cadence, Siemens EDA, or equivalent
Familiarity with data analytics, telemetry, and AI-assisted design methodologies
Strong cross-functional leadership and communication skills
Applicants must be eligible to access export-controlled information as defined under applicable law.
Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

Skills

Python
Tcl
Shell scripting
Linux
ASIC/SoC development lifecycle
Data analytics
Telemetry
AI-assisted design methodologies

Experience Level

5-10 years of related professional experience
3-5 years of experience
5+ years of experience in ASIC CAD, EDA, design methodology, or infrastructure engineering
8+ years preferred

Education Level

Bachelor’s degree in Computer Science, Electrical Engineering or related fields
Master’s degree
PhD in Computer Science, Electrical Engineering or related fields

Salary/Compensations

129,100 - 191,030 USD per annum

Benefits

Employee stock purchase plan with a 2-year look back
Family support programs
Robust mental health resources
Recognition and service awards

About the Company

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.
Across enterprise, cloud and AI, carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow.
For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Equal Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.