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About the Role

Normal is building a new class of computing hardware, rethinking the physics of computation from the ground up to unlock performance and efficiency that conventional architectures can't reach. As FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development, and building the test infrastructure for post-silicon bring-up and characterization. Your scope spans the entire FPGA lifecycle - selecting hardware platforms, implementing complex RTL, debugging in the lab, and writing the software that drives it all.

Responsibilities

Lead the selection, procurement, and bring-up of FPGA prototyping platforms for pre-silicon RTL validation and software development.
Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock-domain architectures, CDC bridges, and timing closure on dense designs.
Integrate in-house designs with third-party and vendor IP; serve as the expert on the AMD/Xilinx ecosystem.
Design, implement, and validate high-speed I/O with a focus on PCIe.
Build FPGA-based "tester" designs for silicon bring-up, device characterization, and automated test environments.
Develop the software layer around the hardware, including Python/C++ hardware abstraction, register-map generation, and automated build and regression flows.
Root-cause complex timing and functional issues in real time using ILA/Vivado Analyzer, oscilloscopes, logic analyzers, and BER/eye-diagram characterization of high-speed links.

Requirements

Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware, ideally in an ASIC prototyping, emulation, or high-growth hardware environment.
Expert-level SystemVerilog and/or VHDL for synthesis, with deep proficiency in Xilinx Vivado (synthesis, place & route, timing closure, IP catalog).
Hands-on experience implementing and debugging PCIe, plus AXI/AHB, SPI, UART, JTAG, and other common interfaces.
Strong Python for automation, test, and build tooling.
Strong board-level bring-up and lab debugging skills on real hardware.
Startup mindset: ability to work independently, pivot quickly, and tackle ambiguous problems spanning hardware, software, and physics.

Skills

SystemVerilog
VHDL
Xilinx Vivado
PCIe
AXI
AHB
SPI
UART
JTAG
Python
ILA/Vivado Analyzer
Oscilloscopes
Logic Analyzers
Cocotb
UVM
OSVVM
hls4ml
FINN
GitLab CI
Docker

Location

New York
San Francisco
Copenhagen
Seoul
London

Work Type

Onsite

Experience Level

Industry experience

About the Company

Normal Computing is the frontier AI lab for silicon, building a new paradigm to power human progress by reducing the cost of intelligence by 1,000x.
Our AI platform for collaborative silicon engineering is deployed with the world's largest semiconductor companies, and we are building our own unconventional silicon.
We work as one team across New York, San Francisco, Copenhagen, Seoul, and London being directly forward-deployed with many of our customers.

Equal Opportunity

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.