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About the Role

Responsible for the front-end design and verification of design blocks for cores, including architecture definition, logic design, synthesis, constraint development, and verification through simulation and formal methods. You will design logic blocks from system requirements and debug designs using Verilog simulation.

Responsibilities

• Front end design and verification of design blocks for cores
• Architecture definition
• Logic design
• Synthesis
• Constraint development
• Design verification through simulation
• Formal verification
• Analysis of timing from physical implementation
• Design logic blocks from systems requirements documents
• Simulate and debug designs with Verilog simulation

Requirements

• Familiarity with entire ASIC design and implementation flow
• Ability to work independently as well as part of a large team spanning multiple geographies
• Experience with complete ASIC or standard product implementation flow from RTL synthesis, timing analysis / closure
• Proficiency with TCL/Perl scripting
• Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler
• Timing analysis experience with Primetime for high frequency designs and advanced technology nodes/libraries
• Understanding of liberty LIB models for timing
• Formal verification (Synopsys Formality / Cadence Conformal)
• Spyglass Lint
• Power analysis of RTL and gate level netlists
• Familiarity with DFT (design for test) and scan methodology
• Version control (svn, git, etc)

Skills

• Verilog simulation
• TCL/Perl scripting
• Synopsys Design Compiler/ DC topo
• Cadence RTL compiler
• Primetime
• Synopsys Formality
• Cadence Conformal
• Spyglass Lint
• DFT
• scan methodology
• svn
• git

Location

• USA

Work Type

• Full-time

Experience Level

• Bachelors and 8+ years of related experience
• Masters degree and 6+ years of related experience

Education Level

• BS/MS in Electrical or Computer Engineering or equivalent

Salary/Compensations

• USD 121,900.00 To USD 195,000.00

Benefits

• Discretionary annual bonus
• Competitive new hire equity grant
• Annual equity awards
• Medical plans
• Dental plans
• Vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays
• Paid sick leave
• Vacation time
• Paid Family Leave
• Other leaves of absence

About the Company

• Global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

Equal Opportunity

• We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.
• We will also consider qualified applicants with arrest and conviction records consistent with local law.