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About the Role

Define, develop, and drive CPU timing closure for Oryon CPU Cores. Work with microarchitecture and RTL design teams to develop timing constraints and drive implementation to meet power, area, and performance goals. Code scripts for STA native tools to enable CPU timing infrastructure and methodology impacting multiple CPU projects. Collaborate with Qualcomm central timing technology & methodology team and interact with CPU implementation team to drive PPA goals. Grow professionally working on industry-leading technology nodes N2/N3.

Responsibilities

STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores.
Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
Find root cause of timing miscorrelation at different design levels in functional and test mode, and propose solutions.
Evaluate multiple timing methodologies/tools on different designs and technology nodes.
Technical writing and communication skills.
Willingness to work in a cross-collaborative environment.
Familiarity with digital flow design implementation RTL to GDS: ICC, Innovus, PT/Tempus.

Requirements

Excellent automation skills using TCL/Perl/Python.
Ability to develop/work on automation scripts with the given spec to develop CPU STA signoff flow/methodology.
History of framework/tool/utility development is preferred.
Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling.
Hands-on experience with STA tools - Prime-time, Tempus.
Experience in driving timing convergence at Chip-level and Hard-Macro level.
In-depth knowledge of crosstalk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling.
Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus).
Basic knowledge of device physics.

Skills

TCL
Perl
Python
CPU STA signoff flow/methodology
STA timing analysis
AOCV/POCV concepts
CTS
Timing constraints
Latch transparency handling
0-cycle path handling
Multi-cycle path handling
Prime-time
Tempus
Chip-level timing convergence
Hard-Macro level timing convergence
Crosstalk noise analysis
Signal Integrity analysis
Layout Parasitic Extraction
Feed through handling
ASIC back-end design flows
ICC2
Innovus
Device physics

Location

NUVIA is now part of Qualcomm

Work Type

Full-time

Experience Level

2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience with a Bachelor's degree.
1+ year of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience with a Master's degree.
PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.

Education Level

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.

Salary/Compensations

$122,500.00 - $183,700.00

Benefits

Competitive annual discretionary bonus program.
Opportunity for annual RSU grants.
Highly competitive benefits package designed to support success at work, at home, and at play.

About the Company

Qualcomm Technologies, Inc. is an engineering group focused on CPU Engineering.
NUVIA, now part of Qualcomm, aims to reimagine silicon and create computing platforms that transform the industry.
The company offers opportunities to work with talented engineers on designs that push the envelope on performance, energy efficiency, and scalability.

Equal Opportunity

Qualcomm is an equal opportunity employer.
Qualcomm is committed to providing an accessible process for individuals with disabilities during the application/hiring process.
Qualcomm is committed to making its workplace accessible for individuals with disabilities.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.