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About the Role

Principal-level Silicon Frontend Architect with deep expertise in RTL design methodology, reusable IP architectures, and RTL quality signoff frameworks for large-scale ASIC and SoC development. This role involves defining scalable frontend design methodologies, combining methodology leadership with hands-on RTL execution, and driving lint-first RTL development, IP reuse strategies, and automated frontend quality frameworks.

Responsibilities

Lead architecture, development, and deployment of RTL design methodologies and frontend design flows across IP, subsystem, and SoC programs.
Define and enforce RTL quality signoff frameworks, including lint, CDC, and static analysis integrated into CI-driven development flows.
Drive lint-first design adoption and establish standardized RTL coding guidelines and quality metrics across engineering teams.
Architect and scale reusable IP platforms and configurable RTL frameworks to enable efficient multi-program silicon development.
Develop and optimize frontend design flows integrating static analysis, simulation, and synthesis readiness checks.
Maintain ~50% hands-on RTL design involvement, contributing to microarchitecture development and critical silicon blocks.
Build and deploy automation frameworks and CI/CD pipelines to improve design productivity, regression efficiency, and quality tracking.
Collaborate cross-functionally with design, CAD, verification, and physical implementation teams to optimize frontend workflows and silicon readiness.
Identify methodology gaps and drive continuous improvement in design processes, tools, and infrastructure, including exploration of AI-assisted design techniques.
Drive innovation in AI-enabled RTL design and frontend methodologies, evaluating opportunities for machine learning to enhance design quality, automation, and development efficiency.

Requirements

Deep expertise in SystemVerilog/Verilog RTL design, microarchitecture definition, and implementation for complex ASIC and SoC designs.
Strong experience in high-performance block design, subsystem integration, and scalable RTL architecture across IP and SoC levels.
Proven leadership in defining and deploying enterprise-scale RTL design methodologies and frontend CAD architectures.
Expert in lint-first RTL development methodologies using SpyGlass and Synopsys VC SpyGlass / VC Lint for RTL quality signoff.
Extensive knowledge of structural RTL validation, CDC analysis, and static quality gates for pre-silicon design signoff.
Strong background in IP reuse architecture, including reusable RTL frameworks, standardized interfaces, and multi-program reuse strategies.
Experience in low-power RTL design methodologies, including UPF-aware design, power domains, isolation, and retention strategies.
Proficiency in frontend EDA tools including RTL simulators (VCS, Xcelium, Questa), linting, CDC, and synthesis integration flows.
Strong expertise in automation and infrastructure development using Python, scripting, CI/CD pipelines, and design quality dashboards.
Strong interest in AI-driven silicon design methodologies, with focus on applying AI/ML to improve RTL design productivity, intelligent linting, design space exploration, and next-generation frontend automation.

Skills

RTL design methodology
Reusable IP architectures
RTL quality signoff frameworks
ASIC development
SoC development
Lint-first RTL development
IP reuse strategies
Automated frontend quality frameworks
SystemVerilog
Verilog
Microarchitecture definition
RTL implementation
High-performance block design
Subsystem integration
Scalable RTL architecture
Frontend CAD architectures
SpyGlass
Synopsys VC SpyGlass
VC Lint
Structural RTL validation
CDC analysis
Static quality gates
IP reuse architecture
Reusable RTL frameworks
Standardized interfaces
Multi-program reuse strategies
Low-power RTL design methodologies
UPF-aware design
Power domains
Isolation strategies
Retention strategies
RTL simulators (VCS, Xcelium, Questa)
Linting
CDC
Synthesis integration flows
Automation
Infrastructure development
Python
Scripting
CI/CD pipelines
Design quality dashboards
AI-driven silicon design methodologies
AI/ML techniques

Location

Austin, Texas

Work Type

On-Site
Hybrid

Experience Level

10+ years of experience

Education Level

BS/MS, Electrical Engineering, Computer Science or similar

Salary/Compensations

The salary range for this position is dependent on various factors including, but not limited to, location, and the candidate’s combination of job-related knowledge, qualifications, skills, education, training, and experience.

Benefits

Choice of three medical plan options
Dental plan option
Company credits towards medical and dental premiums
Ericsson US 401(k) Plan with automatic 3% company contribution
Ericsson match $1 for every $1 on the first 3% of eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay
Company credits towards basic life insurance and basic accidental death and dismemberment coverage
Company credits towards short-term and long-term disability coverage
Option to participate in Ericsson’s Stock Purchase Plan
15 days of accrued vacation
Up to 3 personal days per year
11 annual holidays
8 hours of volunteer time
80 hours of sick time annually
Up to 16 weeks of paid maternity leave
6 weeks of parental or adoption leave at 100% of pay
Financial wellness programs
Educational assistance
Matching gifts
Recognition programs

About the Company

The Team is part of the Ericsson Silicon engineering unit, which develops state of the art ASIC's and FPGA's targeting the newest technology nodes for Ericsson's 5G telecommunication product portfolio.
This department offers many opportunities for career growth and a large base of knowledge to learn from.

Equal Opportunity

Ericsson uses a merit-based hiring approach that values people with different experiences, perspectives and skillsets.
We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team.
Ericsson is proud to be an Equal Opportunity employer.
If you need assistance or to request an accommodation due to a disability, please contact Ericsson at hr.direct.americas@ericsson.com.