Impress employers and recruiters.
Choose from hundreds of resume examples.

Target Resume Now

About the Role

We are looking for a SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required. The role involves following systematic quality metrics driven ATPG pattern generation. Hands-on knowledge of synthesis, verification, and debugging Verilog testbenches is highly desirable.

Responsibilities

Scan chain insertion
Compression scan insertion
LBIST and other scan technologies
Memory build-in self-test (MBIST)
Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
Debug and Analysis of failures to improve fault coverage
Verification of ATPG testbenches and debugging root cause of simulation mis-compares
Work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers

Requirements

US citizenship Required
Prior 2-10 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
Intimate knowledge of DFT insertion flows
Basic scan chain insertion using synthesis or other software tools
Experience in compression scan insertion, LBIST and other scan technologies
Intimate knowledge of memory build-in self-test (MBIST)
Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
Debug and Analysis of failures to improve fault coverage
Verification of ATPG testbenches and debugging root cause of simulation mis-compares
Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687
Knowledge of timing analysis and equivalency checks would be added bonus
Ability to work in collaborative team environment
Prior experience with Cadence tools and flows is highly desirable
Should be able to finish DFT tasks independently
Strong problem-solving skills
Exhibit discipline, thoroughness, and methodical approach in solving problems
Self-driven and committed individual who can work in a fast-paced project environment

Skills

Design for Test (DFT)
Scan chain insertion
Compression scan technologies
Memory built-in self-test (MBIST)
Automatic Test Pattern Generation (ATPG)
Synthesis
Verification
Debugging Verilog testbenches
JTAG 1149.1/6
IEEE1500
IEEE1687
Timing analysis
Equivalency checks
Problem-solving

Location

Work Type

Full-time

Experience Level

2-10 years

About the Company

Cadence plays a critical role in creating the technologies that modern life depends on.
We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.
Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Equal Opportunity

Cadence is committed to equal employment opportunity throughout all levels of the organization.
Cadence is proud to be an equal opportunity employer.
All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.