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About the Role

We are seeking a TPU and AMD GPU performance engineer to enhance vLLM's capabilities on non-NVIDIA accelerators, ensuring efficient and broad AI inference across diverse hardware platforms. You will optimize backends, kernels, and runtime paths, working at the intersection of inference systems, compilers, and hardware architecture.

Responsibilities

• Build and optimize AMD GPU and TPU backends, kernels, compiler integrations, runtime paths, and benchmarking infrastructure.
• Improve inference paths such as attention, GEMM, sampling, KV-cache, communication-heavy operations, and model serving on non-NVIDIA hardware.
• Work at the boundary of inference systems, kernels, compilers, and hardware architecture.

Requirements

• Bachelor's degree or equivalent experience in computer science, engineering, machine learning systems, hardware systems, compilers, or similar.
• Hands-on experience optimizing workloads on AMD GPUs, TPUs, or another non-NVIDIA accelerator stack.
• Experience with AMD ecosystem tools such as ROCm, HIP, Triton, CK, AITER, or equivalent GPU performance libraries and tooling.
• Experience with TPU, XLA, JAX, Pallas, or related compiler and runtime tooling for accelerator workloads.
• Ability to optimize ML inference paths such as attention, GEMM, sampling, KV-cache, fused kernels, backend runtimes, or communication-heavy operations.
• Strong performance profiling and benchmarking discipline, including tokens/second, latency, throughput, correctness parity, hardware counters, and reproducible measurement methodology.
• Ability to navigate immature tooling, incomplete documentation, backend-specific rough edges, and cross-platform performance differences without getting stuck.
• Experience with vLLM, SGLang, TensorRT-LLM, ATOM, JAX-based serving framework, or other LLM inference systems.
• Deep understanding of inference architecture and serving tradeoffs, including batching, KV-cache, decoding, prefill/decode scheduling, and backend performance constraints.
• Experience with compiler technologies such as XLA, MLIR, LLVM, Triton, Pallas, or other compiler / kernel DSLs, including lowering, fusion, and backend code generation.
• Knowledge of quantization techniques such as MXFP8, MXFP4, mixed precision, or hardware-specific numeric formats, and the ability to reason about accuracy/performance tradeoffs.
• Experience with distributed inference performance, including communication, memory movement, hardware topology, and scale-out bottlenecks across multi-accelerator workloads.
• Open-source contributions to vLLM, JAX/XLA, ROCm, Triton, PyTorch, compiler projects, or related ML systems infrastructure.
• Delivered measurable AMD GPU performance improvements on critical inference paths using ROCm, HIP, Triton, CK, AITER, or equivalent tools.
• Implemented or significantly improved TPU inference support using JAX, XLA, Pallas, or related compiler/runtime tooling.
• Built cross-platform benchmarking infrastructure for TPU, AMD GPU, or other non-NVIDIA accelerator targets.
• Implemented automated performance regression detection across representative models, architectures, workloads, or hardware backends.
• Collaborated with AMD, Google TPU ecosystem teams, accelerator vendors, or platform teams to ship backend optimizations or vendor-supported inference paths.

Skills

• TPU
• AMD GPU
• vLLM
• ROCm
• HIP
• Triton
• CK
• AITER
• XLA
• JAX
• Pallas
• MLIR
• LLVM
• MXFP8
• MXFP4
• distributed inference
• performance profiling
• benchmarking
• compiler integration
• kernel optimization
• runtime optimization
• quantization techniques
• inference architecture
• serving tradeoffs
• batching
• KV-cache
• decoding
• prefill/decode scheduling
• backend performance
• communication-heavy operations
• model serving
• heterogeneous hardware platforms
• cross-platform performance
• automated performance regression detection
• vendor collaboration

Location

• San Francisco, California
• Remote in US

Work Type

• Remote

Experience Level

• Senior

Education Level

• Bachelor's degree or equivalent experience

Salary/Compensations

• $200,000 - $400,000 USD + equity

Benefits

• Generous health, dental, and vision benefits
• 401(k) company match

About the Company

• Inferact's mission is to grow vLLM as the world's AI inference engine and accelerate AI progress by making inference cheaper and faster.
• Founded by the creators and core maintainers of vLLM, we sit at the intersection of models and hardware—a position that took years to build.