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About the Role

We are seeking a Technical Lead Design Verification Engineer with extensive experience in UVM and C/C++ for verification tasks. The role involves utilizing high-level programming languages to interact with System Verilog and UVM environments for RTL simulation, CoSimulation, and Emulation.

Responsibilities

• Integrate C/C++ in System Verilog environments using DPI/PLI.
• Utilize scripting tools (Perl/Python) to automate verification infrastructure.
• Develop infrastructure and tests in a hybrid directed and constrained random environment.
• Develop test plans and related test sequences in UVM to generate stimuli.
• Collaborate with RTL designers to debug failures.
• Develop user-controlled random constraints in transaction-based verification methodology.
• Write assertions and cover properties, and analyze coverage data.
• Utilize Verification IPs from third-party vendors for communication protocols such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc.
• Develop VIP abstraction layers to simplify and scale verification deployments.
• Perform S/W debugging for SoC based designs in kernel/device-drivers/u-boot.
• Conduct Physical Layer, Link Layer, and Transaction Layer verification for PCIe protocol.
• Verify memory technologies like DDR4/DDR5/HBM.
• Utilize FPGA-based verification/emulation.

Requirements

• Strong academic and technical background in electrical engineering.
• Professional attitude with the ability to prioritize dynamic tasks.
• Ability to plan and prepare for customer meetings in advance.
• Ability to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude.
• Ability to think and act fast with the customer in mind.
• Authorized to work in Canada and start immediately.

Skills

• UVM
• C/C++
• System Verilog
• Perl
• Python
• DPI/PLI
• PCI-Express
• Ethernet
• Infiniband
• DDR
• NVMe
• USB
• FPGA

Location

• Canada

Work Type

• Full-time

Experience Level

• 8+ years

Education Level

• Bachelor's in EE required
• Master's preferred

Salary/Compensations

• $140,000 CAD - $175,000 CAD

About the Company

• Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
• Collaborates with hyperscalers and ecosystem partners to enable organizations to unlock the full potential of modern AI.
• Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the COSMOS software suite.
• Offers custom connectivity solutions business that complements its standards-based portfolio.

Equal Opportunity

• Actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.