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About the Role

Drive high-speed connectivity solutions by building and leading a team responsible for micro-architecture and implementation of front-end digital design, including RTL development, synthesis, IP integration, and block-level verification for high-performance ASICs.

Responsibilities

• Deliver micro-architecture and implementation of front-end digital design
• Develop RTL
• Perform synthesis
• Integrate IP
• Perform block-level verification for high-performance ASICs
• Develop and support PCIe or Ethernet Switch products

Requirements

• Strong academic and technical background in electrical engineering
• 10+ years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications
• 5+ years’ experience managing a team of RTL design engineers
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision
• Entrepreneurial, open-mind behavior and can-do attitude
• Authorized to work in Canada and start immediately
• Hands-on, thorough knowledge of high-speed DPSs and SerDes equilizers
• Hands-on, thorough knowledge of high-speed protocols like CXL/PCIe, Ethernet, or DDR
• Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
• Experience with Cadence and/or Synopsys digital design tools/flows
• Experience with scripting and automation, with a strong methodology background
• Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
• Familiarity with UVM based design verification
• Silicon bring-up and debug expertise
• Small-geometry CMOS (≤28nm) design
• Firmware development with C-language
• Scripting with Python or other equivalent programming languages

Skills

• Low-power design techniques
• SerDes DSP design
• Equalizer optimization for power and area efficiency
• CXL/PCIe (Gen 3 and above)
• Ethernet
• DDR
• High-speed DPSs
• SerDes equilizers
• High-speed protocols
• Architecture
• RTL
• Simulations
• Synthesis
• Timing closure
• GLS
• DFT
• Cadence digital design tools/flows
• Synopsys digital design tools/flows
• Scripting
• Automation
• Design for test (DFT)
• Stuck-at and transition scan test insertion
• UVM based design verification
• Silicon bring-up
• Debug
• Small-geometry CMOS (≤28nm) design
• Firmware development
• C-language
• Python

Location

• Canada

Work Type

• Full-time

Experience Level

• 10+ years’ experience supporting or developing complex SoC/silicon products
• 5+ years’ experience managing a team of RTL design engineers

Education Level

• Bachelor’s degree in EE
• Master’s degree preferred

Salary/Compensations

• CAD 200,000 – CAD 250,000

About the Company

• Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
• By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI.
• Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
• The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.

Equal Opportunity

• We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.