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About the Role

Develop implementation flows and methodologies for high-performance, low-power designs on advanced technology nodes, focusing on improving Power, Performance, and Area (PPA) in taped-out designs for next-generation products.

Responsibilities

• Lead and contribute to cross-functional efforts solving complex physical design challenges across multiple IPs, projects, and technology nodes.
• Develop and maintain RTL-to-GDS methodologies, including floorplanning, synthesis, place-and-route, static timing analysis, signoff, and chip assembly.
• Optimize EDA tools, flows, and custom CAD solutions to improve PPA, runtime, automation, and engineering productivity.
• Partner with physical verification, RC extraction, timing, and DFT teams, driving innovative ML-based approaches to design optimization.

Requirements

• BS/MS in Electrical or Computer Engineering, or equivalent experience.
• 5+ years in Physical Design and CAD methodology development.
• Strong track record of building implementation flows for high-performance, low-power designs on advanced nodes.
• Proven ability to deliver measurable PPA improvements in silicon.
• Hands-on experience with industry-standard EDA tools like Fusion Compiler for synthesis, place-and-route, static timing analysis, and signoff closure.
• Proficiency in hierarchical design flows and physical design verification.
• Proficiency in scripting (Tcl, Python, Perl) for automation, robustness, and efficiency.
• Eligibility to access U.S. export-controlled technology, potentially requiring a U.S. export license based on citizenship/permanent residency status.

Skills

• Physical Design
• CAD methodology development
• EDA tools (Fusion Compiler)
• Synthesis
• Place-and-route
• Static timing analysis
• Signoff closure
• Hierarchical design flows
• Physical design verification
• Tcl
• Python
• Perl
• ML-based approaches to design optimization

Location

• Santa Clara, CA
• Fort Collins, CO
• Austin, TX

Work Type

• Hybrid

Experience Level

• Seasoned
• 5+ years in Physical Design and CAD methodology development
• Various experience levels

Education Level

• BS in Electrical or Computer Engineering
• MS in Electrical or Computer Engineering
• Equivalent experience

Salary/Compensations

• $100k - $500k (including base and variable compensation targets)

Benefits

• Highly competitive compensation package
• Benefits

About the Company

• Tenstorrent leads the industry in cutting-edge AI technology, revolutionizing performance, ease of use, and cost efficiency.
• AI redefines computing, requiring solutions that unify innovations in software models, compilers, platforms, networking, and semiconductors.
• The diverse team developed a high-performance RISC-V CPU from scratch.
• The company values collaboration, curiosity, and a commitment to solving hard problems.
• Tenstorrent is passionate about AI and building the best AI platform possible.

Equal Opportunity

• Tenstorrent is an equal opportunity employer.